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Features
■ Low power CapSense
®
block
❐ Configurable capacitive sensing elements
❐ Supports combination of CapSense buttons, sliders,
touchpads, and proximity sensors
■ Powerful Harvard-architecture processor
❐ M8C processor speeds running up to 12 MHz
❐ Low power at high speed
❐ Operating voltage: 2.4 V to 5.25 V
❐ Industrial temperature range: –40 °C to +85 °C
■ Flexible on-chip memory
❐ 8 KB flash program storage 50,000 erase/write cycles
❐ 512-Bytes SRAM data storage
❐ Partial flash updates
❐ Flexible protection modes
❐ Interrupt controller
❐ In-system serial programming (ISSP)
■ Complete development tools
❐ Free development tool (PSoC Designer™)
❐ Full-featured, in-circuit emulator, and programmer
❐ Full-speed emulation
❐ Complex breakpoint structure
❐ 128 KB trace memory
■ Precision, programmable clocking
❐ Internal ±5.0% 6- / 12-MHz main oscillator
❐ Internal low speed oscillator at 32 kHz for watchdog and sleep
■ Programmable pin configurations
❐ Pull-up, high Z, open-drain, and CMOS drive modes on all
GPIOs
❐ Up to 28 analog inputs on all GPIOs
❐ Configurable inputs on all GPIOs
❐ 20-mA sink current on all GPIOs
❐ Selectable, regulated digital I/O on port 1
• 3.0 V, 20 mA total port 1 source current
• 5 mA strong drive mode on port 1 versatile analog mux
❐ Common internal analog bus
❐ Simultaneous connection of I/O combinations
❐ Comparator noise immunity
❐ Low-dropout voltage regulator for the analog array
■ Additional system resources
❐ Configurable communication speeds
• I2C: selectable to 50 kHz, 100 kHz, or 400 kHz
• SPI: configurable between 46.9 kHz and 3 MHz
❐ I2C slave
❐ SPI master and SPI slave
❐ Watchdog and sleep timers
❐ Internal voltage reference
❐ Integrated supervisory circuit

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When you are ready to test the hardware configuration or move
on to developing code for the project, you perform the

“Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system. The
generated code provides application programming interfaces
(APIs) with high-level functions to control and respond to
hardware events at run-time and interrupt service routines that
you can adapt as needed.
A complete code development environment allows you to
develop and customize your applications in either C, assembly
language, or both.
The last step in the development process takes place inside
PSoC Designer’s debugger (access by clicking the Connect
icon). PSoC Designer downloads the HEX image to the ICE
where it runs at full speed. PSoC Designer debugging

capabilities rival those of systems costing many times more. In

addition
to traditional single-step, run-to-breakpoint, and watch-

variable
features, the debug interface provides a large trace buffer and
allows you to define complex breakpoint events. These include
monitoring address and data bus values, memory locations, and
external signals.

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Features
■ Low power, configurable CapSense
®
❐ Configurable capacitive sensing elements
❐ operating voltage
❐ Operating voltage: 2.4 V to 5.25 V
❐ Low operating current
• Active 1.5 mA (at 3.0 V, 12 MHz)
• Sleep 2.8 µA (at 3.3 V)
❐ Supports up to 25 capacitive buttons
❐ Supports one slider
❐ Up to 10 cm proximity sensing
❐ Supports up to 28 general-purpose I/O (GPIO) pins
• Drive LEDs and other outputs
❐ Configurable LED behavior (fading, strobing)
❐ LED color mixing (RBG LEDs)
❐ Pull-up, high Z, open-drain, and CMOS drive modes on all
GPIOs
❐ Internal ±5.0% 6 or12 MHz main oscillator
❐ Internal low-speed oscillator at 32 kHz
❐ Low external component count
• No external crystal or oscillator components
• No external voltage regulator required
■ High-performance CapSense
❐ Ultra fast scan speed —1 kHz (nominal)
❐ Reliable finger detection through 5 mm thick acrylic
❐ Excellent EMI and AC noise immunity
■ Industry best flexibility
❐ 8 KB flash program storage 50,000 erase and write cycles
❐ 512-bytes SRAM data storage
❐ Bootloader for ease of field reprogramming
❐ Partial flash updates
❐ Flexible flash protection modes
❐ Interrupt controller
❐ In-system serial programming (ISSP)
❐ Free complete development tool (PSoC Designer™)
❐ Full-featured, in-circuit emulator and programmer
• Full-speed emulation
• Complex breakpoint structure
• 128 KB trace memory
■ Additional system resources
❐ Configurable communication speeds
❐ I2C slave
❐ SPI master and SPI slave
❐ Watchdog and sleep timers
❐ Internal voltage reference
❐ Integrated supervisory circuit

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Additional System Resources
System resources, some of which are previously listed, provide
additional capability useful to complete systems. Additional
resources include low voltage detection (LVD) and power on
reset (POR). Brief statements describing the merits of each
system resource follow.
■ The I
2
C slave and SPI master-slave module provides 50, 100,
or 400 kHz communication over two wires. SPI communication
over three or four wires runs at speeds of 46.9 kHz to 3 MHz
(lower for a slower system clock).
■ LVD interrupts signal the application of falling voltage

levels,
while the advanced POR circuit eliminates the need for a
system supervisor.
■ An internal 1.8-V reference provides an absolute reference

for
capacitive sensing.
■ The 5 V maximum input, 3 V fixed output, low dropout

regulator
(LDO) provides regulation for I/Os. A register controlled bypass
mode enables the user to disable the LDO.

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Features
■ QuietZone™ Controller
❐ Patented Capacitive Sigma Delta PLUS (CSD PLUS™)
sensing algorithm for robust performance
❐ High Sensitivity (0.1 pF) and best-in-class SNR performance
to support:
• Ideal for proximity solutions
• Overlay thickness of 15 mm for glass and 5 mm plastic
❐ Superior noise immunity performance against conducted and
radiated noise and ultra low radiated emissions
• Reliable and robust touch performance in noisy environments
❐ Standardized user modules for overcoming noise
■ Low power CapSense
®
block with SmartSense™ auto-tuning
❐ Supports a combination of up to 31 buttons or 6 sliders,

proximity sensors
❐ Low average power consumption – 28 A for each sensor at
runtime (wake from sleep and scan sensors every 125 ms)
❐ SmartSense auto-tuning
• Sets and maintains optimal sensor performance during
runtime
• Eliminates system tuning during development and production
• Compensates for variations in manufacturing process
■ Driven shield available on five GPIO pins
❐ Max load of 100 pF at 3 MHz
❐ Frequency range: 375 kHz to 3 MHz
❐ Delivers best-in class water tolerant designs
❐ Robust proximity sensing in the presence of metal objects
■ Powerful Harvard-architecture processor
❐ M8C CPU with a maximum speed of 24 MHz
❐ Operating range: 1.71 V to 5.5 V
• Standby mode: 1.1 µA (typ)
• Deep sleep: 0.1 µA (typ)
❐ Temperature range: –40 °C to +85 °C
■ Flexible on-chip memory
❐ 8 KB flash, 1 KB SRAM
❐ 16 KB flash, 2 KB SRAM
❐ 32 KB flash, 2 KB SRAM
❐ 50,000 flash erase/write cycles
❐ In-system programming capability
■ Four clock sources
❐ Internal main oscillator (IMO): 6/12/24 MHz
❐ Internal low-speed oscillator (ILO) at 32 kHz for watchdog
and sleep timers
❐ RC crystal oscillator
❐ Clock input
■ Programmable pin configurations
❐ Up to 32 general-purpose I/Os (GPIOs)
❐ Dual mode GPIO
❐ High sink current of 25 mA for each GPIO. Total 120 mA
maximum sink current per chip
❐ 5 mA source current on port 0 and 1 and 1 mA on port 2,3
and 4
❐ Configurable internal pull-up, high-Z, and open drain modes
❐ Selectable, regulated digital I/O on port 1
❐ Configurable input threshold on port 1
■ Versatile analog mux
❐ Common internal analog bus
❐ Simultaneous connection of I/O
❐ High power supply rejection ratio (PSRR) comparator
❐ Low-dropout voltage regulator for all analog resources
■ Additional system resources
❐ I2C slave:
• Selectable to 50 kHz, 100 kHz, or 400 kHz
• Selectable clock stretch or forced Nack mode
• Implementation during sleep modes with less than 100 µA
• I2C wake from sleep with hardware address validation
❐ 12 MHz SPI master and slave
❐ Three 16-bit timers
❐ Watchdog and sleep timers
❐ Internal voltage reference
❐ Integrated supervisory circuit
❐ 10-bit incremental analog-to-digital converter (ADC)
❐ Two general-purpose high speed, low power analog comparators
■ Complete development tools
❐ Free development tool (PSoC Designer™)
■ Package options
❐ 16-pin SOIC (150 mil)
❐ 16-pin QFN – 3 × 3 × 0.6 mm
❐ 24-pin QFN – 4 × 4 × 0.6 mm
❐ 32-pin QFN – 5 × 5 × 0.6 mm
❐ 48-pin QFN – 6 × 6 × 0.6 mm
❐ 30-ball WLCSP

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System resources provide additional capability, such as
configurable I2C slave, SPI master/slave communication
interface, three 16-bit programmable timers, various system
resets supported by the M8C low voltage detection and poweron

reset. The merits of each system resource are listed here:
■ The I2C slave/SPI master-slave module provides 50/100/
400 kHz communication over two wires. SPI communication
over three or four wires runs at speeds of 46.9 kHz to 3 MHz
(lower for a slower system clock).
■ The I2C hardware address recognition feature reduces the
already low power consumption by eliminating the need for
CPU intervention until a packet addressed to the target device
is received.
■ The I2C enhanced slave interface appears as a 32-byte RAM
buffer to the external I2C master. Using a simple predefined
protocol, the master controls the read and write pointers into
the RAM. When this method is enabled, the slave does not stall
the bus when receiving data bytes in active mode. For usage
details, see the application note I2C Enhanced Slave Operation
- AN56007.
■ Low-voltage detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced

poweron reset (POR) circuit eliminates the need for a system
supervisor.
■ An internal reference provides an absolute reference for
capacitive sensing.
■ A register-controlled bypass mode allows the user to disable
the LDO regulator.

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CY8C20247S-24LKXI Development Tool Selection
Software
PSoC Designer™
At the core of the PSoC development software suite is
PSoC Designer, used to generate PSoC firmware applications.
PSoC Designer is a Microsoft
®
Windows-based, integrated
development environment for the Programmable System-onChip

(PSoC) devices. The PSoC Designer IDE and application
runs on Windows XP and Windows Vista.
This system provides design database management by project,
in-system programming support, and built-in support for

thirdparty assemblers and C compilers. PSoC Designer also
supports C language compilers developed specifically for the
devices in the PSoC family.

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engineering . Designing with PSoC Designer
The PSoC development process can be summarized in the
following four steps:
1. Select User Modules
2. Configure User Modules
3. Organize and Connect
4. Generate and Verify
Select Components
PSoC Designer provides a library of pre-built, pre-tested
hardware peripheral components called “user modules”. User
modules make selecting and implementing peripheral devices,
both analog and digital, simple.
Configure Components
Each of the User Modules you select establishes the basic
register settings that implement the selected function. They

also
provide parameters and properties that allow you to tailor their
precise configuration to your particular application. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to
correspond to your chosen application. Enter values directly or
by selecting values from drop-down menus. All the user modules
are documented in datasheets that may be viewed directly in
PSoC Designer or on the Cypress website. These user module
datasheets explain the internal operation of the User Module and
provide performance specifications. Each datasheet describes
the use of each user module parameter, and other information
you may need to successfully implement your design.
Organize and Connect
You build signal chains at the chip level by interconnecting

user
modules to each other and the I/O pins. You perform the
selection, configuration, and routing so that you have complete
control over all on-chip resources.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, you perform the

“Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system. The
generated code provides application programming interfaces
(APIs) with high-level functions to control and respond to
hardware events at run time and interrupt service routines that
you can adapt as needed.
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.

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C Language Compilers.  C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices. The
optimizing C compilers provide all the features of C tailored to
the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
PSoC Programmer
PSoC Programmer is flexible enough and is used on the bench
in development and is also suitable for factory programming.
PSoC Programmer works either as a standalone programming
application or operates directly from PSoC Designer. PSoC
Programmer software is compatible with both PSoC ICE Cube
in-circuit Emulator and PSoC MiniProg. PSoC programmer is
available free of cost.

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❐ Patented Capacitive Sigma Delta PLUS (CSD PLUS™)
sensing algorithm for robust performance
❐ High Sensitivity (0.1 pF) and best-in-class SNR performance
to support:
• Ideal for proximity solutions
• Overlay thickness of 15 mm for glass and 5 mm plastic
❐ Superior noise immunity performance against conducted and
radiated noise and ultra low radiated emissions
• Reliable and robust touch performance in noisy environments
❐ Standardized user modules for overcoming noise
■ Low power CapSense
®
block with SmartSense™ auto-tuning
❐ Supports a combination of up to 31 buttons or 6 sliders,

proximity sensors
❐ Low average power consumption – 28 A for each sensor at
runtime (wake from sleep and scan sensors every 125 ms)
❐ SmartSense auto-tuning
• Sets and maintains optimal sensor performance during
runtime
• Eliminates system tuning during development and production
• Compensates for variations in manufacturing proces